JP-A-2009-272435 discloses a circuit board with a built-in semiconductor chip and a method of manufacturing the circuit board.
The semiconductor chip built into the circuit board has via-hole electrodes extending from its front side to its back side. Bumps are formed on the front side of the semiconductor chip, and backside terminals are formed on the back side of the semiconductor chip and connected to the via-hole electrodes. The bumps and the backside terminals are connected to an integrated circuit of the semiconductor chip and serve as electrodes.
The semiconductor chip is mounded in a flip chip manner through the bumps on a core substrate made of glass-reinforced resin. A circuit having connection terminals are formed in the core substrate. The connection terminals of the core substrate are connected to the bumps of the semiconductor chip by ultrasonic bonding. An underfil material is located between the core substrate and the semiconductor chip.
A prepreg layer made of glass-reinforced resin is formed on the core substrate. The prepreg layer has an opening where the semiconductor chip is located.
Wiring layers are formed on the prepreg layer, the semiconductor chip, and the backside of the core substrate. The wiring layer on the prepreg layer and the semiconductor chip is connected to the backside terminals of the semiconductor chip, and the wiring layer on the backside of the core substrate is connected to the circuit of the core substrate.
The circuit board is manufactured by the following method. Firstly, a Si-based semiconductor chip having gold stud pumps on its front side and aluminum terminals on its back side is prepared. The aluminum terminals are connected to via-hole electrodes in the substrate. Further, a core substrate having connection terminals is prepared.
Then, the stud bumps of the semiconductor chip are connected to the connection terminals of the core substrate by ultrasonic bonding. Then, an underfil material is injected between the core substrate and the semiconductor chip and hardened under heat. Further, copper stud bumps are formed on the backside terminals of the semiconductor chip.
Next, a prepreg layer having an opening is stacked on the surface of the core substrate and hardened under pressure and heat. Then, a wiring layer is formed on each side of the core substrate.
US 2008/0017409A corresponding to JP 2007-A-324550 discloses a method of manufacturing a circuit board with a built-in electronic component.
In the method, resin layers including a layer having a conductor pattern on its surface and a layer having a via hole filled with a conductive paste are stacked to form a stacked body in which an electronic component is located.
Then, heat and pressure are applied to the stacked body from its both sides so that thermoplastic resin of the resin layers can be softened. Thus, the resin layers of the stacked body are joined together at a time so that the electronic component can be sealed and encapsulated in the stacked body. At the same time, the conductive paste in the via hole is sintered into an interlayer connection member that serves as an electrode for connecting the conductor patterns.
According to the method disclosed in US 2008/0017409A, the stacked body having the electronic component inside is formed into the circuit board at a time by applying heat and pressure to the stacked body. Therefore, manufacturing process is simplified so that manufacturing time can be reduced.
Recently, in the field of semiconductor chip design, there has been a trend that electrodes are arranged at a fine pitch (i.e., at a narrow pitch) to increase chip integration degree, to increase chip speed, and to reduce chip size. Assuming that a bare semiconductor chip is mounded in a flip chip manner by, the method disclosed in US 2008/0017409A, there is a need to from a via hole having a very small diameter (e. g., several to tens of micrometers) to achieve the fine pitch arrangement and to ensure electrical insulation between adjacent interlayer connection members. It is difficult to form such a small via hole and to fill the small via hole with a conductive paste.
Further, as the via hole is smaller, the amount of the conductive paste in the via hole becomes smaller. As a result, reliability of electrical connection between the interlayer connection member and the conductor pattern may be reduced.
For example, a stud bump is formed on an electrode of the semiconductor chip, and the semiconductor chip is mounded on a substrate by connecting the stud bump on a pad of the substrate. In this case, to prevent adjacent electrodes from being short-circuited, there is a need to connect the stud bump to the pad by solid-phase diffusion bonding as disclosed in JP-A-2009-272435.
Assuming that the above conventional methods are combined to simplify the manufacturing process, stress may be concentrated on the solid-phased stud bump during application of heat and pressure to the stacked body having the semiconductor chip inside. As a result, the semiconductor chip may be damaged by the concentrated stress.